1. Field of the Invention
The present invention relates to a solid-state imaging device and a method of manufacturing a solid-state imaging device. More particularly, the present invention relates to a solid-state imaging device which suppresses diffusion of residual metal elements remained due to planarization processing being performed and suppresses deterioration of sensitivity or an image quality, and a method of manufacturing the solid-state imaging device.
2. Description of Related Art
In recent years, in order to meet the demands for reducing the size and weight and for lowering power consumption for products in which a solid-state imaging device is used, a processing circuit which has been provided in a signal processing device is to be formed in the periphery of a light receiving section of a solid-state imaging device. As a result, a single solid-state imaging device is enabled to perform all processing and the signal processing device is no longer required.
As such a solid-state imaging device, a complementary metal oxide semiconductor (CMOS) solid-state imaging device is particularly known to have advantages for reducing the size and weight as well as the cost, and further, for lowering power consumption. The CMOS solid-state imaging device is formed by providing a peripheral circuit made of a required circuit, in the periphery of a light receiving section in which a photoelectric conversion element having a CMOS structure is formed.
With the progresses of micro-fabrication techniques of a MOS process, it becomes possible easily to have a photoelectric conversion element be miniaturized with higher number of pixels and to have a peripheral circuit be highly integrated. Accordingly, the solid-state imaging device is more and more improved to reduce the size and to have higher number of pixels and higher functions.
As one of the recent micro-fabrication techniques, there has been proposed, for example, a technique of using copper wiring for wiring in a device, in place of related art aluminium wiring. More specifically, because copper has a resistance value lower than that of aluminium and is possible to make a wiring pitch small and a wiring thickness thin, the use of the copper wiring is proposed as one of the miniaturizing techniques. However, since an etching for copper has not been established yet, a dual damascene technique is presently employed, in which a wiring groove is formed and filled with conductive materials such as metals (for example, copper) and then polished by a chemical mechanical polishing (CMP) method to form wiring and a connection section at the same time (for example, refer to Japanese Patent Application Publication No. 2003-324189).
On the other hand, there still remains an issue of mounting multi-functional circuits on the solid-state imaging device without sacrificing the image quality performance as an imaging device.
As an imaging device, the solid-state imaging device is required to suppress the deterioration (for example, so-called up-shift output values due to dark currents) of the image quality of reproduced images. In the case where copper is used as a material for the wiring, if copper leaks from the copper wiring and diffuses into an interlayer insulation film and a silicon substrate and then reaches a light receiving section of a photoelectric conversion element, the diffused copper behaves as impurity contamination to cause deterioration of the image quality such as increasing dark currents (so-called white spots). Accordingly, in order to suppress factors which cause deterioration of the image quality and a threshold shifting of MOS transistors of peripheral circuits, it is necessary to form a diffusion protection film so as to cover the upper surface of the copper wiring after the copper wiring is formed by the dual damascene.
A method of manufacturing the CMOS solid-state imaging device in which the copper wiring is formed by the dual damascene will be described below with reference to the drawings.
In the method of manufacturing the CMOS solid-state imaging device in which the copper wiring is formed by the dual damascene, as shown in FIG. 5A, first, an element isolation film 102 is formed on an N-type silicon substrate 101 by shallow trench isolation (STI). In addition, a well region (not shown) is formed, and phosphorus (P), arsenic (As), boron (B), boron difluoride (BF2), which are impurities, are selectively filled into a region to be an N-type MOS transistor or a P-type MOS transistor, and next, a gate oxide film 103 of a transistor is formed by thermal oxidation, after that, a gate electrode 104 of a transistor is formed.
Next, a sidewall 105 and a high concentration diffusion layer region 106 having an lightly doped drain (LDD) structure are formed by ion implantation and heat treatment, and a light receiving section 107 is formed by filling with impurities.
Further, a silicon nitride film 108 serving as a stopper layer is formed on a surface of the silicon substrate 101 by low-pressure chemical vapor deposition (LPCVD). In order to improve defects of white spots and to progress a driving performance of the MOS transistor, an opening 150 is formed on a part of the silicon nitride film 108 by general-purpose photolithography and etching. After that, an interlayer insulation film 109 is formed on the silicon nitride film 108 (refer to FIG. 5A).
Next, as shown in FIG. 5B, a first connection hole for connecting the high concentration diffusion layer region 106 and a first wiring layer which is described later is formed in the silicon nitride film 108 and the interlayer insulation film 109. After filling the first connection hole with a barrier metal layer 110A containing tantalum nitride and a tungsten electrode layer 110B, polishing is performed on the first connection hole by the CMP to form a first connection section 110.
In addition, a first inter-wiring insulation film 111 is formed and processed by general-purpose photolithography and etching to form a first wiring groove in a region to be copper wiring which is described later. A barrier metal 112A and copper 112B are filled in the first wiring groove and the surplus copper and the surplus barrier metal are polished and removed by the CMP to form a first wiring layer 112. Further, a first diffusion protection film (for example, a silicon carbide film) 113 is formed on the first wiring layer 112 to protect the copper wiring (refer to FIG. 5B).
As shown in FIG. 5C, a second inter-wiring insulation film 114 is formed on the first diffusion protection film 113, and a region to be a second connection section and a second wiring layer is processed by general-purpose photolithography and etching and filled with barrier metals 115A and 116A and copper 115B and 116B, and then the surplus copper and the surplus barrier metal are polished and removed by the CMP to form a second connection section 115 and a second wiring layer 116. Further, a second diffusion protection film (for example, a silicon carbide film) 117 is formed on the second wiring layer 116 to protect the copper wiring (refer to FIG. 5C).
After that, a color resist 118 and an on-chip lens 119 are formed thereon, and thus the CMOS solid-state imaging device can be obtained (refer to FIG. 5D).
It is to be noted that, in the CMOS solid-state imaging device shown in FIGS. 5A to 5D, since layers having different refractive indexes and absorption indexes are stacked on the light receiving section 107, it may cause the deterioration of a light receiving efficiency to the photoelectric conversion element due to attenuation or interference of light. In order to address it, a technique has recently been proposed which opens a diffusion protection film at a predetermined range on the upper region of a photoelectric conversion element.
In other words, according to the proposed technique, by selectively opening the upper region of the light receiving section of the photoelectric conversion element, deterioration of the light receiving efficiency due to attenuation or interference of light is suppressed and light is allowed to enter into the light receiving section favorably, even materials having different refractive indexes and different absorption indexes for the light transmitted are used to make the diffusion protection film, which is provided to protect diffusion from materials used for the wiring.
Specifically, after the diffusion protection film 117 is formed to protect the copper wiring in the second wiring layer as shown in FIG. 5C, the light receiving region of the photoelectric conversion element is opened by general-purpose photography and etching to form an opening region 120A. Sequentially, the opening region 120A is filled with a CVD oxide film 121 and polished by the CMP to remove the surplus CVD oxide film 121, thereby forming an opening 120 of the upper region of the light receiving section of the photoelectric conversion element (refer to FIG. 6A). After that, a color resist 118 and an on-chip lens 119 are formed thereon, and thus the CMOS solid-state imaging device can be obtained (refer to FIG. 6B).